The present invention generally relates to providing a low power autozero capability for a pixel amplifier to remove noise in the information collected by image sensors, which are commonly found in digital scanners, copiers, facsimile machines, or other document generating or reproducing device. More specifically, the present invention removes amplifier offset without dramatically increasing chip power and without slowing down the pixel read out rate to provide a clear readout free of the noise. The present invention is particularly applicable to color input imaging devices or systems.
The present application incorporates by reference U.S. Pat. Nos. 5,081,536 and 5,493,423.
Image sensor arrays typically comprise a linear array of photosensors which raster scan an image bearing document and convert the microscopic image areas viewed by each photosensor to image signal charges. Following an integration period, the image signal charges are amplified and transferred as an analog video signal to a common output line or bus through successively actuated multiplexing transistors. One example of such an array is a charged-coupled device (CCD).
For high-performance image sensor arrays, a preferred design includes an array of photosensors of a width comparable to the width of a page being scanned, to permit one-to-one imaging generally without the use of reductive optics. In order to provide such a xe2x80x9cfull-widthxe2x80x9d array, however, relatively large silicon structures must be used to define the large number of photosensors. A preferred technique to create such a large array is to align several butted silicon chips, each chip defining a small linear array thereon. The term xe2x80x9cbuttedxe2x80x9d in this application refers to both xe2x80x9cbuttedxe2x80x9d and xe2x80x9cnear butted.xe2x80x9d
The silicon chips which are butted to form a single full-width array are typically created by first creating the circuitry for a plurality of individual chips on a single silicon wafer. The silicon wafer is then cut or xe2x80x9cdiced,xe2x80x9d around the circuit areas to yield discrete chips. Typically, the technique for dicing the chips includes a combination of chemical etching and mechanical sawing. On each chip, the photosensors are spaced with high resolution from one end of a chip to the other; the length of each diced chip from one end of the array thereon to the other requires precision dicing. It would be desirable to dice each individual chip with a precise dimension along the linear array of photosensors, so that, when a series of chips are butted end-to-end to form a single page-width linear array, there is a minimum disruption of spacing from an end photosensor on one chip to a neighboring photosensor at the end of a neighboring chip. Ideally, the spacing, or pitch, across an entire full-width linear array should be consistent regardless of the configuration of silicon chips forming the array.
Preferably, the full-width array extends the entire length of a document, such as eleven inches. Usually, the full-width array is used to scan line by line across the width of a document with the document being moved or stepped lengthwise in synchronism therewith. A typical architecture for such a sensor array is given, for example, in U.S. Pat. No. 5,473,513. When the original document moves past the full-width array, each of the photosensors converts reflected light from the original image into electrical signals. The motion of the original image perpendicular to the linear array causes a sequence of signals to be output from each photosensor, which can be converted into digital data.
With the gradual introduction of color-capable products into the office equipment market, it has become desirable to provide scanning systems which are capable of converting light from full-color images into separate trains of image signals, each train representing one primary color. In order to obtain the separate signals relating to color separations in a full-color image, one technique is to provide on each semiconductor chip multiple parallel linear arrays of photosensors, each of the parallel arrays being sensitive to one primary color. Typically, this arrangement can be achieved by providing multiple linear arrays of photosensors which are physically identical except for a selectively transparent primary-color overlay over the photosensitive areas, or xe2x80x9cphotosites,xe2x80x9d for that linear array. In other words, the linear array which is supposed to be sensitive to red light only will have a selectively transparent red layer placed on the photosites thereof, and such would be the case for a blue-sensitive array, a green-sensitive array, or any other color-sensitive array. These selectively transparent layers are also referred to as absorption filter layers, because they selectively adsorb or block light having certain frequencies or wavelengths from reaching the photosensitive areas. Although it is preferable to use three linear arrays, any number of linear arrays can be used. As the chips are exposed to an original full-color image, only those portions of the image, which correspond to particular primary colors, will reach those photosensors assigned to the primary color.
The most common substances for providing these selectively transparent filter layers over the photosites are polyimide or acrylic. For example, polyimide is typically applied in liquid form to a batch of photosensor chips while the chips are still in undiced, wafer form. After the polyimide liquid is applied to the wafer, the wafer is centrifuged to provide an even layer of a particular polyimide. In order to obtain the polyimide having the desired primary-color-filtering properties, it is well known to dope the polyimide with either a pigment or dye of the desired color, and these dopants are readily commercially available. When it is desired to place different kinds of color filters on a single chip, a typical technique is to first apply an even layer of polyimide over the entire main surface of the chip (while the chip is still part of the wafer) and then remove the unnecessary parts of the filter by photo-etching or another well known technique. Typically, the entire filter layer placed over the chip is removed except for those areas over the desired set of photosites. Acrylic is applied to the wafer in a similar manner. After the chips are mounted to a substrate as taught in U.S. Pat. No. 5,473,513, a glass cover is placed over the chips and mounted on the substrate to provide physical protection of the chips.
As indicated above, image sensor arrays typically comprise at least one linear array of photosites which scan an image bearing document and convert the microscopic image areas viewed by each photosite to image signal charges. Following an integration period, the image signal charges are amplified and transferred to a common output line or bus through successively actuated multiplexing transistors.
In the scanning process, bias and reset charges are applied to each photosite cell in a predetermined time sequence during each scan cycle. Where a two stage transfer circuit is provided with each cell for transferring the image signal charges from the photosites, the bias charge is applied to each photosite through a bias charge injection transistor coupled to a node between the photosite and the input to the two stage transfer circuit. However, even if the transistors between the photodiode in the photosite and its associated amplifier are reset with each scan cycle, the particular amplifier associated with the photosite, which includes any number of transistors within it, is not always similarly reset. The transistors within the amplifier may retain residual charges thereon between scan cycles, and the cumulative effect of these residual charges remaining within the amplifier could be a source of noise on the output signals coming out of the amplifiers. It is therefore desirable to provide a system in which not only are the transistors between the photodiode and the amplifier reset, but wherein the transistors within the amplifier itself are periodically reset to retain charges between each scan cycle of known value. In this way circuit elements particularly transistors, within each amplifier will start from known states with every scan cycle, and the amplifier itself will not become a source of noise. This is intended to provide uniformity by causing critical nodes within the amplifier associated with the sensor to settle to known charge values or known voltage after each signal is passed through.
However, there is a problem with the prior art in that the prior art does not reset all of the circuit elements including the transistors in the amplifier itself at the same time, in addition, the voltage level has several components in it, including at least the signal voltage (based on image information from the photosite) and a dark offset voltage, or nominal starting operating voltage. The problem is that this voltage level may also contain some dark nonuniformity, or fixed pattern noise, from pixel to pixel, if the voltage buffering in the two stage transfer circuit and amplifier are done on a per pixel basis as is often done in CMOS sensors. Fixed pattern noise is caused by random process variations from pixel to pixel.
In order to solve this problem and enhance image quality, Correlated Double Sampling (CDS) or Double Sampling (DS) can be used to remove this fixed pattern noise, especially during the relative long row readout time on area image sensors. If maximum speed is not needed, DS can also be done at the pixel readout rate on linear sensors with a 2xc3x97impact on readout time. However, this is very time consuming. Therefore, there is a need to provide a method and apparatus to reset the circuit elements at the same time and to eliminate the noise caused by the dark offset voltage.
According to one embodiment of the present invention, there is provided a photosensor array including a plurality of photosites, wherein an amplifier is associated with each photosite and each amplifier includes a plurality of transistors. Each amplifier includes autozeroing transistors for autozeroing at low power to remove voltage offsets in the amplifier. A transfer circuit is associated with each photosite for transferring a charge on the photosite to a reset node interposed between the photosite and amplifier. The photosites in the photosensor array may be photodiodes. The photosensor array may include a linear array of photosites or multiple parallel linear arrays of photosites. The amplifier includes a differential pair of transistors and a matched load pair of transistors, wherein the differential pair of transistors and the matched load of transistors operate at the same VGSNxe2x88x92VTN. The amplifier includes a dummy transistor associated with the autozeroing transistors, wherein the dummy transistor compensates the autozeroing transistors. The amplifier is autozeroed during a reset time. The transistors of the amplifier comprise one of CMOS or Bipolar. The photosensor array further comprises means for selectively causing the amplifier to output a charge from the reset node as an output signal.
A digital imaging system for generating an image from output image signals comprising: a photoreceptor; a plurality of charging units charging the photoreceptor; a plurality of exposure units receiving the image signals and exposing the photoreceptor to place a latent image on the photoreceptor based on the image signals; a scanner for scanning the images, generating the output image signals and transmitting the output image signals to the exposure units, wherein the scanner includes a photosensor array having a plurality of photosites, each photosite being associated with an amplifier, which includes autozeroing transistors for autozeroing at low power to remove voltage offsets in the amplifier; each photosite being associated with a transfer circuit for transferring a charge on the photosite to a reset node interposed between the photosite and amplifier; and each photosite being associated with a means for selectively causing the amplifier to output a charge from the reset node as output image signals; a plurality of developer structures, each developer structure being connected to a corresponding dispenser, each dispenser having a different toner, and each developer structure applying toner to the photoreceptor; a transfer unit transferring the toner on the photoreceptor to a support material; a fusing unit fusing the toner to the support material; and a cleaner cleaning the photoreceptor after the support material has passed through the transfer unit. The photosites are photodiodes.
A method of operating an amplifier at low power mode for removing voltage offsets in the amplifier, comprising the steps of: applying a reference voltage to the input node of the amplifier to prepare the amplifier for voltage offset removal; selecting the low power mode; autozeroing the amplifier at low power mode by selecting the autozero clock; deselecting the autozero clock while the reference voltage is still at the input node and the amplifier is in the low power mode; applying a signal to the input node of the amplifier; and selecting the high power mode of the amplifier and read out the signal without voltage offset.